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Simscope + Verilog

Diagnose, assign, and resolve simulation errors

Simscope automatically groups errors into Signatures

Simscope captures all types of Verilog and SystemVerilog errors: Signature Details

Sample SystemVerilog error

ncsim: *E,TRNULLID: NULL pointer dereference.

Sample Verilog compile error

ncvlog: *E,INTOVF (test.v,17|34): bit overflow during conversion from text [2.5(IEEE)] (10 bits).

→ Signature #100:

ncvlog ... INTOVF test.v ... bit overflow during conversion from text ... IEEE ... bits

Sample Verilog assertions

ncsim: *E,ASRTST (syn_fifo_psl.v,108): (time 49 NS)     Assertion fifo_tb.fifo.ERROR_readempty has failed

→ Signature #1011:

ncsim ... ASRTST syn_fifo_psl.v ... time ... NS Assertion [HIER].ERROR_readempty has failed

Sample UVM errors

UVM_ERROR        @ 305412ps   [uvm_test_top.subsys2.ovc_ref_model.scoreboard]: wr:<0051> wr_data:[0x00000168] rd:5'b011x1 rd_data:[0x000003e5]

→ Signature #240:

UVM_ERROR ... [HIER].scoreboard wr ... wr_data ... rd ... rd_data ...

Sample UVM error

    if (tx_pkt.mac_dst_addr != rx_pkt.mac_dst_addr) begin
        `uvm_error(get_name(), $psprintf("MAC_DST_ADDR MISMATCH!, Exp=0x%0x, Act=0x%0x",
                                         tx_pkt.mac_dst_addr, rx_pkt.mac_dst_addr))

Work on groups of errors, rather than each individual error.


Advanced analysis

Rerun failures

For further debugging, users can easily rerun failures, with exact reproducibility:

Tracking PASS

Simscope also tracks passing simulations for analysis:


Simscope is simulator-independent:

More integrations